1. Field of the Invention
The present invention relates to a semiconductor field effect transistor, and more particularly to a switch element using a field effect transistor whose conduction and nonconduction are controlled.
2. Background of the Invention
Switch elements are commonly used in multipurpose integrated wireless circuits for switching the path of the RF signal between parts of the circuits. Antenna switch is a typical application of such RF switch elements, in which the switch connects an antenna with transmitting and receiving circuits. In order to prevent the loss of transmitted signal and its leakage into the receiving part, the antenna switches are required to have low insertion loss and high isolation in their ON and OFF states, respectively. Although a number of device types can provide such functionalities, the most commonly used devices for the antenna switch in monolithic microwave integrated circuits (MMIC's) are the multi-gate field effect transistors (FET), or in particular, the multi-gate pseudomorphic high-electron-mobility transistors (pHEMT).
An issue of concern in using multi-gate FETs as switch elements is the linearity of the switch operating in its OFF state. FIG. 1 depicts the cross section of a typical dual-gate FET structure, comprising, in general, a substrate 101, a buffer layer 102, a channel layer 103, a low conducting layer 104, a high conducting layer 105, two ohmic electrodes 106, and two of Schottky electrodes 107 disposed between the two ohmic electrodes 106. The two ohmic electrodes 106 contact ohmic-contacted to the channel layer 103 via the high conducting layer 105, functioning as the source and the drain terminals of the FET. The two Schottky electrodes 107, on the other hand, act as multi-gate electrodes of the FET, which contact to the low conducting layer 104 via recess etching. In the dual-gate FET device, there exists a conductive region 108 between the two adjacent gate electrodes 107. The conductive regions 108 only have minor effects when the dual-gate FET is operating in its ON state. However, when the dual-gate FET is operating in its OFF state, the channel is closed and the conductive region 108 between the two adjacent gates 107 becomes floating. At OFF state, the floating conductive region 108 will be biased at a voltage just below the threshold voltage of the channel irrespective of the magnitude of the reverse voltage applied between gate and ohmic electrodes. This induces the low operation margin of the FET in preventing a large input signal from leaking through the FET. At the same time, due to the large voltage dependence in the capacitance component near the threshold voltage, the large nonlinearity is induced in the FET at OFF-state, and thus would generate large distortion when the antenna switch handles high RF powers.
To improve the OFF-state linearity of a multi-gate FET, the inter-gate conductive regions must be electrically connected. However, the spacing between gates is usually narrower than the width of a resistor component or a contact wire. If the inter-gate spacing was increased substantially for connecting the conductive regions to a resistor, the ON-state resistance and hence the insertion loss of the antenna switch will increase. Therefore, the inter-gate spacing must be maintained as narrow as possible. To solve this problem, the conductive regions of a multi-gate FET are usually connected to a balance resistor at one end of the gate electrodes, where the inter-gate spacing is made wider in order to enable the formation of electrical contacts, as shown illustrated in FIGS. 2A and 2B. By connecting to the balance resistor, the voltage of the conductive region between gates in the OFF state is fixed at a voltage close to source and drain, thereby improving the OFF-state linearity of the switch. However, as the inter-gate spacing is shrunk, the resistance of the conductive regions between two adjacent gates becomes larger. As a result, the voltage drop along the conductive region due to gate leakage current becomes appreciable, leading to OFF-state linearity degradation. The OFF-state linearity will be further degraded at higher operation temperatures, where the gate leakage current becomes even larger.
Therefore, there is a need to provide a new design for a multi-gate FET, of which the connection of the inter-gate conductive regions to a balance resistor, with improved OFF-state linearity while retaining a low insertion loss and a small total chip size.